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|Tuesday August 30||09:00 – 10:00 CEST||Hybrid Silicon III-V Lasers||Dr. Ray Beausoleil (Hewlett Packard Labs, USA)|
|Tuesday August 30||14:30 – 15:30 CEST||Bringing Silicon Photonics Products to Market||Dr. Yannick De Koninck (Luxtera, USA)|
|Wednesday August 31||09:00 – 10:00 CEST||Silicon Photonics Technology Platforms||Dr. Amit Khanna (imec, Belgium)|
|Wednesday August 31||10:00 – 11:00 CEST||Silicon Photonics at ST Microelectronics||Dr. Charles Baudot ( ST Micro. France)|
|Wednesday August 31||11:30 – 12:30 CEST||Packaging of sillicon photonic ICs||Dr. Peter O' Brien (Tyndall National Institute, Ireland)|
|Thursday September 1||14:30 – 15:30 CEST||Silicon Photonics at Thales Research and Technology||Dr. Jerome Bourderionnet (Thales Research & Technology, France)|
Abstracts of lectures
Hybrid Silicon III-V Lasers (Dr. Ray Beausoleil (HP Labs, USA): Moore's Law has set great expectations that the performance/price ratio of commercially available semiconductor devices will continue to improve exponentially at least until the end of this decade, but the physics of the metal wires that connect transistors and chips places stringent limits on the performance of integrated circuits. Therefore, over the past decade, much work has been done on Si-compatible global photonic interconnect architectures, but a cost-effective scalable laser source remains a critical challenge. A promising approach to the problem of fabricating compact, highly efficient laser sources for high-volume, low-cost data networks is the heterogeneous integration of III-V membranes onto an SOI substrate, coupling the high single-pass direct-bandgap gain of III-V materials with the CMOS compatibility of high-index-contrast silicon waveguides. Through both wafer bonding and direct growth of InP and InAlGaAs quantum-well materials on SOI, this approach has been used to fabricate hybrid Fabry-Perot lasers, disk lasers, and single-mode microring lasers. In this lecture, we will discuss: Common wafer-bonding approaches for hybrid lasers; challenges faced by hybrid laser technologies for Datacom applications; harnessing MOS effects for laser tuning and chirp correction; hybrid laser devices based on quantum dots; and prospects for integration and scaling of hybrid laser technologies.
Bringing Silicon Photonics Products to Market (Dr. Yannick De Koninck, Luxtera, USA): This lecture will elaborate on the different aspects of building silicon photonics products. We will start with an overview of the market in which Luxtera operates and discuss how silicon photonics can be a differentiator for these applications. We will walk through the design process and the need for consolidating standard component designs and models into a design library. Next we’ll give an overview of the assembly process where we’ll follow the journey of a silicon photonics chip from the fab all the way to a working transceiver module. It will become apparent that it take much more than a good optical design to make commercial products: waferscale assembly and test, integration with electronics, reliable light sources, packaging. . . Finally we will take a look at where the industry is going next and how silicon photonics fits into that roadmap.
Silicon Photonics Technology Platforms (Dr. Amit Khanna, imec, Belgium): Not available
Silicon Photonics at ST Microelectronics (Charles Baudot ( ST Micro. France): There is a recurring statement about silicon photonics which points out that one major breakthrough of that technology is the CMOS foundry processes compatibility. The objective of this course is to understand better the rationale about CMOS foundry compatibility, how silicon photonics can benefit from it and the associated constraints of that strategy. It occurs that for decades, the core of industrial semiconductor manufacturing has been driven by silicon processing. Consequently, vast fabrication skills and material expertise were acquired during that period. Still now, silicon remains a solid candidate for contemporary Moore nodes. Moreover, few derivative integrated technologies have emerged from silicon processing, typically: bipolar electronics, MEMS and imaging devices. Nowadays, silicon state-of-the-art manufacturing occurs on 300mm wafer substrates using DUV-193nm immersion lithography to process transistors for the 14nm technological node. Thus, both high volume and high precision processing can be achieved with the same technology. Therefore, even if such dimensions and volumes are not yet targeted for silicon photonics, it makes no doubt that silicon CMOS foundry knowhow is giving a huge start pulse to silicon photonics as it has been the case for other derivative technologies.
Packaging of sillicon photonic ICs (Dr. Peter O' Brien, Tyndall National Institute, Ireland): Europe has invested heavily in programmes to advance Si-PIC technologies, resulting in the rapid growth of highly innovative PIC-based solutions for a wide range of applications and markets. Much of this activity has focused on the Si-PIC chip, and significant challenges remain in the area of chip integration and packaging. These challenges block users from commercialising full system solutions, and greatly limit the uptake of Si-PIC technologies. This presentation will give a wide overview of key optical, electronic, thermal and mechanical requirements for packaging of Si-PIC chips. The presentation will include a review of key packaging equipment and processes, and will provide information about critical packaging design rules which can greatly reduce the complexity and cost of packaging tasks.
Silicon Photonics at Thales Research and Technology (Dr. Jerome Bourderionnet (Thales Research & Technology, France): To be announced